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IDT74ALVCHR16601 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 18-BIT UNIVERSAL IDT74ALVCHR16601 BUS TRANSCEIVER WITH 3-STATE OUTPUTS AND BUS-HOLD
* 0.5 MICRON CMOS Technology * Typical tSK(o) (Output Skew) < 250ps * ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) * VCC = 3.3V 0.3V, Normal Range * VCC = 2.7V to 3.6V, Extended Range * VCC = 2.5V 0.2V * CMOS power levels (0.4 W typ. static) * Rail-to-Rail output swing for increased noise margin * Available in SSOP, TSSOP, and TVSOP packages
FEATURES:
DESCRIPTION:
This 18-bit universal bus transceiver is built using advanced dual metal CMOS technology. The transceiver combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB and CLKENBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. Output enable OEAB is active low. When OEAB is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, CLKBA and CLKENBA. The ALVCHR16601 has series resistors in the device output structure which will significantly reduce line noise when used with light loads. This driver has been designed to drive 12mA at the designated threshold levels. The ALVCHR16601 has "bus-hold" which retains the inputs' last state whenever the input goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors.
DRIVE FEATURES: APPLICATIONS:
* Balanced Output Drivers: 12mA * Low Switching Noise
* 3.3V high speed systems * 3.3V and lower voltage computing systems
FUNCTIONAL BLOCK DIAGRAM
OEAB CLKENAB CLKAB LEAB LEBA CLKBA CLKENBA OEBA A1
1
56
55
2
28
30
29
27
CE
3
1D C1 CLK
54
B1
CE 1D C1 CLK
TO 17 OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
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(c) 1999 Integrated Device Technology, Inc.
JUNE 1999
DSC-4491/2
IDT74ALVCHR16601 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
OEAB LEAB A1 GND A2 A3 VCC A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC A16 A17 GND A18 OEBA LEBA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 CLKENAB CLKAB B1 GND B2 B3 VCC B4 B5 B6 GND B7 B8 B9 B10 B11 B12 GND B13 B14 B15 VCC B16 B17 GND B18 CLKBA CLKENBA
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description Max VTERM(2) VTERM(3) TSTG IOUT IIK IOK ICC ISS Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature DC Output Current Continuous Clamp Current, VI < 0 or VI > VCC Continuous Clamp Current, VO < 0 Continuous Current through each VCC or GND -0.5 to +4.6 -0.5 to VCC+0.5 -65 to +150 -50 to +50 50 -50 100
Unit V V C mA mA mA mA
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC.
CAPACITANCE (TA = +25C, F = 1.0MHz)
Symbol CIN COUT CI/O Parameter(1) Input Capacitance Output Capacitance I/O Port Capacitance Conditions VIN = 0V VOUT = 0V VIN = 0V Typ. 5 7 7 Max. 7 9 9 Unit pF pF pF
NOTE: 1. As applicable to the device type.
FUNCTION TABLE(1,2)
Inputs CLKENAB X X X H L L L OEAB H L L L L L L LEAB X H H L L L L CLKAB X X X X L or H Ax X L H X L H X Outputs Bx Z L H B(3) L H B(3)
SSOP/ TSSOP/ TVSOP TOP VIEW
PIN DESCRIPTION
Pin Names OEAB OEBA LEAB LEBA CLKAB CLKBA Ax Bx CLKENAB CLKENBA Description A-to-B Output Enable Input (Active LOW) B-to-A Output Enable Input (Active LOW) A-to-B Latch Enable Input B-to-A Latch Enable Input A-to-B Clock Input B-to-A Clock Input A-to-B Data Inputs or B-to-A 3-State Outputs(1) B-to-A Data Inputs or A-to-B 3-State Outputs(1) A-to-B Clock Enable Input (Active LOW) B-to-A Clock Enable Input (Active LOW)
NOTES: 1. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, CLKBA, and CLKENBA. 2. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High Impedance = LOW-to-HIGH transition 3. Output level before the indicated steady-state input conditions were established.
NOTE: 1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
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IDT74ALVCHR16601 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = -40C to +85C
Symbol VIH VIL IIH IIL IOZH IOZL VIK VH ICCL ICCH ICCZ ICC Parameter Input HIGH Voltage Level Input LOW Voltage Level Input HIGH Current Input LOW Current High Impedance Output Current (3-State Output pins) Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current VCC = 2.3V, IIN = -18mA VCC = 3.3V VCC = 3.6V VIN = GND or VCC One input at VCC - 0.6V, other inputs at VCC or GND VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V VCC = 3.6V VCC = 3.6V VI = VCC VI = GND VO = VCC VO = GND Test Conditions Min. 1.7 2 -- -- -- -- -- -- -- -- -- Typ.(1) -- -- -- -- -- -- -- -- -0.7 100 0.1 Max. -- -- 0.7 0.8 5 5 10 10 -1.2 -- 40 V mV A A A A V Unit V
Quiescent Power Supply Current Variation
--
--
750
A
NOTE: 1. Typical values are at VCC = 3.3V, +25C ambient.
BUS-HOLD CHARACTERISTICS
Symbol IBHH IBHL IBHH IBHL IBHHO IBHLO
NOTES: 1. Pins with Bus-Hold are identified in the pin description. 2. Typical values are at VCC = 3.3V, +25C ambient.
Parameter(1) Bus-Hold Input Sustain Current Bus-Hold Input Sustain Current Bus-Hold Input Overdrive Current VCC = 3V VCC = 2.3V VCC = 3.6V
Test Conditions VI = 2V VI = 0.8V VI = 1.7V VI = 0.7V VI = 0 to 3.6V
Min. - 75 75 - 45 45 --
Typ.(2) -- -- -- -- --
Max. -- -- -- -- 500
Unit A A A
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IDT74ALVCHR16601 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol VOH Parameter Output HIGH Voltage VCC = 2.3V VCC = 2.7V VCC = 3V VOL Output LOW Voltage VCC = 2.3V to 3.6V VCC = 2.3V VCC = 2.7V VCC = 3V Test Conditions(1) VCC = 2.3V to 3.6V IOH = - 0.1mA IOH = - 4mA IOH = - 6mA IOH = - 4mA IOH = - 8mA IOH = - 6mA IOH = - 12mA IOL = 0.1mA IOL = 4mA IOL = 6mA IOL = 4mA IOL = 8mA IOL = 6mA IOL = 12mA Min. VCC - 0.2 1.9 1.7 2.2 2 2.4 2 -- -- -- -- -- -- -- Max. -- -- -- -- -- -- -- 0.2 0.4 0.55 0.4 0.6 0.55 0.8 V Unit V
NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = - 40C to + 85C.
OPERATING CHARACTERISTICS, TA = 25C
VCC = 2.5V 0.2V Symbol CPD CPD Parameter Power Dissipation Capacitance Outputs enabled Power Dissipation Capacitance Outputs disabled Test Conditions CL = 0pF, f = 10Mhz Typical 56 12 VCC = 3.3V 0.3V Typical 63 13 Unit pF
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IDT74ALVCHR16601 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS(1)
VCC = 2.5V 0.2V Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPZH tPZL tSU tSU tSU tSU tH tH tH tH tW tW tSK(O) Propagation Delay Ax to Bx or Bx to Ax Propagation Delay LEAB to Bx or LEBA to Ax Propagation Delay CLKAB to Bx or CLKBA to Ax Output Enable Time OEAB to Bx or OEBA to Ax Output Disable Time OEAB to Bx or OEBA to Ax Set-up Time, data before CLK Set-up Time, data before LE, CLK HIGH Set-up Time, data before LE, CLK LOW Set-up Time, CLKEN before CLK Hold Time, data after CLK Hold Time, data after LE, CLK HIGH Hold Time, data after LE, CLK LOW Hold Time, CLKEN after CLK Pulse Width, LE HIGH Pulse Width, CLK HIGH or LOW Output Skew(2) 2.3 2 1.3 2 0.7 1.3 1.7 0.3 3.3 3.3 -- -- -- -- -- -- -- -- -- -- -- -- 2.4 1.6 1.2 2 0.7 1.6 2 0.5 3.3 3.3 -- -- -- -- -- -- -- -- -- -- -- -- 2.1 1.6 1.1 1.7 0.8 1.4 1.7 0.6 3.3 3.3 -- -- -- -- -- -- -- -- -- -- -- 500 ns ns ns ns ns ns ns ns ns ns ps 1 4.2 -- 5.1 1.6 4.7 ns 1.1 6.3 -- 6.6 1.1 5.6 ns 1.2 5.9 -- 6.3 1.4 5.4 ns 1 5.5 -- 5.8 1 5.1 ns Parameter Min. 150 1 Max. -- 4.8 VCC = 2.7V Min. 150 -- Max. -- 5.1 VCC = 3.3V 0.3V Min. 150 1 Max. -- 4.4 Unit MHz ns
NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = - 40C to + 85C. 2. Skew between any two outputs of the same package and switching in the same direction.
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IDT74ALVCHR16601 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
VIH VT 0V VOH VT VOL VIH VT 0V
ALVC Link
TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS
Symbol VLOAD VIH VT VLZ VHZ CL VCC(1)= 3.3V0.3V VCC(1)= 2.7V 6 2.7 1.5 300 300 50
VCC 500 Pulse Generator
(1, 2)
SAME PHASE INPUT TRANSITION
VCC(2)= 2.5V0.2V 2 x Vcc Vcc Vcc / 2 150 150 30
Unit V V V mV mV pF
VLOAD Open GND
tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION
tPHL
6 2.7 1.5 300 300 50
tPHL
Propagation Delay
ENABLE CONTROL INPUT tPZL OUTPUT SWITCH NORMALLY CLOSED LOW tPZH OUTPUT SWITCH NORMALLY OPEN HIGH VLOAD/2 VT tPHZ VT 0V tPLZ DISABLE VIH VT 0V VLOAD/2 VLZ VOL VOH VHZ 0V
ALVC Link
VIN D.U.T.
VOUT
RT
500 CL
ALVC Link
Test Circuit for All Outputs
DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns. 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2ns; tR 2ns.
NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
Enable and Disable Times
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL
SWITCH POSITION
Test Open Drain Disable Low Enable Low Disable High Enable High All Other Tests Switch VLOAD GND Open
VIH INPUT VT 0V VOH OUTPUT 1 VT VOL VOH OUTPUT 2 tPLH2 tPHL2
ALVC Link
tSU
tH
tREM
tSU
tH
VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V
ALVC Link
Set-up, Hold, and Release Times
tPLH1
tPHL1
LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE
VT
tSK (x)
tSK (x)
VT VOL
VT
ALVC Link
Pulse Width
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
Output Skew - tSK(X)
NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
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IDT74ALVCHR16601 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT ALVC X XX Bus-Hold Temp. Range XX Family XX XXX Device Type Package
PV PA PF 601 R16 H 74
Shrink Small Outline Package Thin Shrink Small Outline Package Thin Very Small Outline Package 18-Bit Universal Bus Transceiver with 3-State Outputs Double-Density, 12mA Bus-Hold -40C to +85C
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for Tech Support: logichelp@idt.com (408) 654-6459
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